1. Field of the Invention
This invention relates generally to electronic memory systems, and relates more particularly to a local system and method for efficiently implementing a double data rate memory architecture.
2. Description of the Background Art
Implementing efficient methods for managing data is a significant consideration for designers and manufacturers of contemporary electronic devices. However, managing data storage and retrieval operations in an electronic device may create substantial challenges for designers of electronic networks. For example, enhanced demands for increased device functionality, bandwidth, and performance during data transfer operations may require more system processing power and require additional hardware resources. An increase in processing or hardware requirements may also result in a corresponding detrimental economic impact due to increased production costs and operational inefficiencies.
Furthermore, enhanced device capability to perform various advanced data handling operations may provide additional benefits to a system user, but may also place increased demands on the control and management of the various components in the electronic device. For example, an enhanced electronic device that effectively accesses, processes, and displays digital video data may benefit from efficient data storage and retrieval techniques because of the large amount and complexity of the digital data involved.
Memory speed is a significant feature in most electronic devices, and is thus an important consideration for both device users and device manufacturers. An electronic device with a higher memory speed is generally able to handle data transfer operations and processes more rapidly than an electronic device having a lower memory speed, so modern electronic devices are typically designed with maximum memory speed and throughput as an important engineering goal.
Memory speeds are significantly affected by the clock frequency of a particular electronic device, with higher clock frequencies usually resulting in higher memory speeds. In general, a clock signal is distributed to various memory circuits within a computer system to control timing of the device""s memory components, to thereby synchronize the data transfer processes. Typically, the clock signal consists of a series of pulses having a specified frequency and specified voltage levels. Each clock pulse includes a rising edge and a falling edge, however, conventional electronic devices, and design synthesis tools typically utilize only a single edge of the clock pulse to synchronize the data transfer operations.
Due to growing demands on system resources and substantially increasing data magnitudes, it is apparent that developing new and effective memory architectures is a matter of importance for the related electronic technologies. Therefore, for all the foregoing reasons, implementing efficient methods for managing data remains a significant consideration for designers, manufacturers, and users of contemporary electronic devices.
In accordance with the present invention, a system and method are disclosed for efficiently implementing a double data rate memory architecture. In one embodiment, a memory device may preferably be implemented to include a decoder, an input/output circuit, and a memory core. The memory core may preferably include a matrix of low-footprint memory cells that are configured in alternating even cell rows and odd cell rows. The memory cells are designed with precharge sensing mechanisms in order to utilize the speed and area of the memory core.
In practice, initially, the decoder may preferably receive a memory address from an address source for accessing one or more horizontal cell rows in the memory core to perform a read operation or a write operation. In response, the memory device preferably may determine a current clock edge state of a memory clock. In accordance with the present invention, the memory clock preferably may comprise a periodic clock pulse that includes a falling edge and a rising edge.
If the current clock edge state is synchronized with a falling edge of the memory clock and the memory device is performing a read operation, then precharge mechanisms preferably begin precharging memory cells in the odd cell rows of the memory core. In either a read operation or a write operation, if the current clock edge state is synchronized with a falling edge of the memory clock, then the decoder preferably determines whether an even memory address has been received from the foregoing address source. If an even memory address has not been received from the address source, then the memory device preferably aborts the data transfer operation.
However, if an even memory address has been received from the address source, then the decoder preferably may activate an appropriate even write word line or even read word line that corresponds to the received even memory address, to thereby select an appropriate even cell row in the memory core. In a read operation, a multiplexor in the input/output circuit preferably may select an appropriate even read bit line or even write bit line for accessing the selected horizontal cell row of the memory core.
In a write operation, the input/output circuit may access the selected horizontal cell row of the memory core by an appropriate even read bit line or even write bit line based upon the clock edge, and may temporarily buffer the transfer data using a local buffer mechanism in the input/output circuit. Finally, the input/output circuit preferably may either perform a write operation to provide transfer data from a data source to the selected horizontal cell row, or may alternately perform a read operation to provide the transfer data from the selected horizontal cell row to a data destination.
In contrast to the foregoing process (which preferably occurs at a falling edge of the memory clock), if the current clock edge state is synchronized with a rising edge of the memory clock and the memory device is performing a read operation, then precharge mechanisms preferably begin precharging memory cells in the even cell rows of the memory core. In either a read operation or a write operation, if the current clock edge state is synchronized with a rising edge of the memory clock, then the decoder preferably determines whether an odd memory address has been received from the foregoing address source. If an odd memory address has not been received from the address source, then the memory device preferably is not selected and no data is read or written to the memory cells.
However, if an odd memory address has been received from the address source, then the decoder preferably may activate an appropriate odd write word line or odd read word line that corresponds to the received even memory address, to thereby select an appropriate odd cell row of the memory core. In a read operation, a multiplexor in the input/output circuit preferably may select an appropriate odd read bit line or odd write bit line for accessing the selected horizontal cell row of the memory core.
In a write operation, the input/output circuit may access the selected horizontal cell row of the memory core by an appropriate odd read bit line or odd write bit line, and temporarily buffer the transfer data using a local buffer mechanism in the input/output circuit. Finally, the input/output circuit preferably may either perform a write operation to provide the transfer data from a data source to the selected horizontal cell row, or may alternately perform a read operation to provide the transfer data from the selected horizontal cell row to a data destination.
The foregoing procedure may then be repeated to alternately perform further data transfer operations to appropriate even horizontal rows or odd horizontal rows of the memory core, in accordance with the present invention. In addition, in certain embodiments, the foregoing procedure may readily be implemented so that the memory device accesses even cell rows on a rising edge of the memory clock, and conversely accesses odd cell rows on a falling edge of the memory clock. The present invention therefore provides a local system and method for more efficiently and effectively implementing a double data rate memory architecture.